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| QS5100 Digital FX LSI 1. General Description The QS5100 is a high quality Effect processor LSI that can produce the effects of reverb, chorus, echo, vibrato, tremolo, wahwah, and flanger with a 5 band-equalizer. All functions can be controlled by an external 8bit MCU, making it possible for the QS5100 to be applied to a wide variety of applications. Making the QS5100 the best solution for external guitar effectors, car audio, PA and hardware effect modules. 2. Features * High resolution of up to 32k ~ 48kHz sampling rate * Supports 8 bit MCU or Serial EEPROM interface for stand alone mode. * 5 band EQ on digital output * Supports 256k words EDO DRAM for delay. * Low power operation 2.7V ~ 3.6V * Support for 16/18/20/22/24 bits Codec I/F * Supports reverb, chorus, echo, wah wah, flanger, tremolo, vibrato * Compact thin package 64 LQFP (10 X 10mm) * f = 8.192 ~ 12.288 MHz * Low power consumption under 10uA in power down mode * IDDOP < 50 mA * Can be assign CODEC I/F (Left or Right Justified) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 QS5100 Datecode KOREA 44 43 42 41 40 39 38 37 36 35 34 33 64P LQFP 10 X 10mm 0.5 pitch QS5100 3. Pin Description PIN NO P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 PAD NAME CPU_DATA[0] CPU_DATA[1] CPU_DATA[2] CPU_DATA[3] CPU_DATA[4] CPU_DATA[5] VDD VSS CPU_DATA[6] CPU_DATA[7] CPU_REB PAD TYPE PC3B03U PC3B03U PC3B03U PC3B03U PC3B03U PC3B03U PVDF PV0F PC3B03U PC3B03U PC3B03U I/O I/O I/O I/O I/O I/O I/O P P I/O I/O I/O Digital FX LSI DESCRIPTION CPU Data I/O for Normal Mode. Serial EEPROM Data I/O for Stand Alone Mode. CPU Data I/O for Normal Mode. Serial EEPROM Clock for Stand Alone Mode. CPU Data I/O for Normal Mode. Set[0] for Stand Alone Mode. CPU Data I/O for Normal Mode. Set[1] for Stand Alone Mode. CPU Data I/O for Normal Mode. Set[2] for Stand Alone Mode. CPU Data I/O for Normal Mode. Set[3] for Stand Alone Mode. Power Ground CPU Data I/O for Normal Mode. Set[4] for Stand Alone Mode. CPU Data I/O for Normal Mode. Set[5] for Stand Alone Mode. Data Read Enable for Normal Mode. Used for external data read operation, functions on active low. First Serial Peripheral Interface CS for Stand Alone Mode. P12 CPU_WEB PC3B03U I/O Data Write Enable for Normal Mode. Used for external data write operation, functions on active low. First Serial Peripheral Interface Clock for Stand Alone Mode. P13 CPU_AB0 PC3B03U I/O Address Data Select for Normal Mode. Used to distinguish between Address and Data. Low for Address, High for Data. First Serial Peripheral Interface Data for Stand Alone Mode P14 CSB PC3D21 I QS5100 Chip Select. Data Read/Write operation possible when `0'. Cannot when `1'. P15 IRQB PC3B03U I/O CPU Interrrupt for Normal Mode. Second Serial Peripheral Interface CS for Stand Alone Mode. P16 P17 P18 SPI2_CLK SPI2_OUT MODE0 PC3B03U PC3B03U PC3D21 I/O I/O I Second Serial Peripheral Interface Clock for Stand Alone Mode. Second Serial Peripheral Interface Data for Stand Alone Mode. System Clock Mode 2X clock is used in System Clock when `0', 1X clock when `1' System Select Mode Normal Mode when `0', Stand Alone Mode when `1' Clock 2X Test Mode Normal mode when `0', Clock 2X test mode when `1' P19 MODE1 PC3D21 I P20 MODE2 PC3D21 I QS5100 Digital FX LSI PIN NO P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 PAD NAME MRSTB XOUT XIN VDD VSS SIN MCLK WCLK BCLK SOUT DRAM_ADDR[4] DRAM_ADDR[5] DRAM_ADDR[6] DRAM_ADDR[7] DRAM_ADDR[8] DRAM_OEB DRAM_UCASB DRAM_LCASB VDD VSS DRAM_ADDR[3] DRAM_ADDR[2] DRAM_ADDR[1] DRAM_ADDR[0] DRAM_RASB DRAM_WEB DRAM_DATA[3] DRAM_DATA[2] DRAM_DATA[1] DRAM_DATA[0] DRAM_DATA[4] DRAM_DATA[5] DRAM_DATA[6] DRAM_DATA[7] DRAM_DATA[8] PAD TYPE PC3D21U PC3X11 PC3X11 PVDF PV0F PC3D21 PC3O03 PC3O03 PC3O03 PC3O03 PC3O03 PC3O03 PC3O03 PC3O03 PC3O03 PC3O03 PC3O03 PC3O03 PVDF PV0F PC3O03 PC3O03 PC3O03 PC3O03 PC3O03 PC3O03 PC3B03U PC3B03U PC3B03U PC3B03U PC3B03U PC3B03U PC3B03U PC3B03U PC3B03U I/O I O I P P I O O O O O O O O O O O O P P O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O DESCRIPTION Master Reset Operates on active low. Crystal Output Crystal Input ( f = 8.192 ~ 12.288 Mhz ) Power Ground Serial Data Input Serial Data System Clock Serial Data Sample Rate Clock Serial Data Bit Clock Serial Data Output DRAM Address DRAM Address DRAM Address DRAM Address DRAM Address DRAM Output Enable DRAM Upper Column Address Strobe DRAM Lower Column Address Strobe Power Ground DRAM Address DRAM Address DRAM Address DRAM Address DRAM Row Address strobe DRAM Write Enable DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs QS5100 Digital FX LSI PIN NO P56 P57 P58 P59 P60 P61 P62 P63 P64 PAD NAME VDD VSS DRAM_DATA[9] DRAM_DATA[10] DRAM_DATA[11] DRAM_DATA[15] DRAM_DATA[14] DRAM_DATA[13] DRAM_DATA[12] PAD TYPE PVDF PV0F PC3B03U PC3B03U PC3B03U PC3B03U PC3B03U PC3B03U PC3B03U I/O P P I/O I/O I/O I/O I/O I/O I/O Power Ground DESCRIPTION DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs DRAM Data Inputs/Outputs QS5100 Digital FX LSI 4. Block Diagram DRAM I/F CPU_DATA[0~7] MCUInterface CPU_RDB CPU_WRB CSB CPU_AB0 IRQB SOUT FX DSP SIN MCLK BCLK WCLK EIL WIL Lin Wah Rin WIR WO TO FO CO ROL Tremolo Flanger Chorus Reverb Echo TIL TIR FIL FIR CIL CIR RIL RIR ROR EIR EOL /EOR BOR WSOR TSOR FSOR CSOR RSOR BOL WSOL TSOL FSOL CSOL RSOL EQOL Data out EQOR EQ QS5100 Digital FX LSI 5. Application 5-1. Typical Hardware Configuration 5-1-1. Using with CODEC Interface C_DATA[0..7] 8bit MICOM ATMEGA-8L or Serial ROM & Select S/W BCLK SIN 16/18/ 20/22/ 24 bits CODEC ROUT LOUT PreAMP AUDIO OUT QS5100 WCLK SOUT MCLK LINE_IN 11.2896 MHz 5-2. Recommended System Reset Circuit and Clock circuit 3.3V XIN 1M XOUT + 20pF 10K 11.2896 MHz KIA7027 3 VCC OUT GND 1 2 MRSTB 47 20pF 1uF * KIA7027 is Voltage Detector made by KEC QS5100 Digital FX LSI 6. Electrical Characteristics 6-1. DC Characteristics Absolute Maximum range ITEMS VDD terminal power supply voltage Operating ambient temperature Carrier temperature Symbol VDD TAOP TCA Min 2.7 -20 -40 Max 3.6 85 125 Unit V C C Industrial Note Recommended operating condition ITEMS VDD terminal power supply voltage Digital input voltage Operating ambient temperature Carrier temperature Symbol VDD VIND TAOP TACA Min 2.7 -0.3 0 -20 Max 3.6 VDD+0.3 70 125 Unit V V C C DC Characteristics ITEMS INPUT Voltage "H" Level INPUT Voltage "L" Level OUTPUT Voltage "H" Level OUTPUT Voltage "L" Level Input Leakage current Input capacity Symbol VIH VIL VOH VOL IL CI 1 Min VDD*0.7 -0.5V VDD - 0.1V VSS + 0.1V 1000 10 Typ Max VDD + 0.5V VDD*0.3 Unit V V V V uA pF QS5100 Digital FX LSI 6-2. AC Characteristics Timing Condition System Clock 24MHz ( Sample Frequency 48 KHz) . 6-2-1. External CPU Interface Timing 6-2-1-1. READ Operation tRC CSB tCS CPU AB0 tACC tAS tCH CPU WEB tWP tWR CPU REB tDS tDH tRE Valid Data tOH Valid Address CPU DATA ITEM Read Cycle Time Access Time from AB0 Chip Enable Setup Time Chip Enable Hold Time AB0 Setup Time Write Pulse Width Write Enable to Read Enable Delay Data Setup Time Data Hold Time Read Enable to Data setup time Hold Time from rising edge of CPU_RDB SYMBOL tRC tACC tCS tCH tAS tWP tWR tDS tDH tRE tOH MIN 136 TYP MAX UNIT ns 113 0 0 0 42 85 5 0 5 5 ns ns ns ns ns ns ns ns ns ns QS5100 Digital FX LSI 6-2-1-2. WRITE Operation tWC CSB tCS CPU AB0 tCH tAS CPU WEB tAH tAW tAP tDS tWP Valid Address tDH Valid Data CPU DATA ITEM Write Cycle Time Chip Enable Setup Time Chip Enable Hold Time AB0 Setup Time AB0 Hold Time Write Pulse Width AB0 High to Write Enable Delay AB0 Preset Time Data Setup Time Data Hold Time SYMBOL tWC tCS tCH tAS tAH tWP tAW tAP tDS tDH MIN 173 0 0 0 0 42 42 42 5 0 TYP MAX UNIT ns ns ns ns ns ns ns Ns ns ns QS5100 6-2-2. CODEC Interface Timing 6-2-2-1. Clock Characteristics ITEM Left/Right Clock Input Bit Clock Input SYMBOL WCLK BCLK MIN 32 2.048 TYP Digital FX LSI MAX 48 3.072 UNIT KHz MHz 6-2-2-2. CODEC Interface Timing in Mode0 (DAC: MSB-First, Right Justified) WCLK Left Channel Right Channel BCLK DOUT 32Bits 32Bits Sign Extension MSB LSB Sign Extension MSB LSB 6-2-2-3. CODEC Interface Timing in Mode1 (DAC: MSB-First, Left Justified) WCLK Left Channel Right Channel BCLK DOUT 32Bits 32Bits MSB LSB Zero MSB LSB Zero QS5100 Digital FX LSI 6-2-2-3. CODEC Interface Timing in Mode0/1 (ADC: MSB-First, Left Justified) WCLK Left Channel Right Channel BCLK DIN 32Bits 32Bits MSB LSB Zero MSB LSB Zero 6-2-2-4. CODEC Interface Timing in Mode2 (DAC/ADC: MSB-First, I2S) WCLK Left Channel Right Channel BCLK DIN/DOUT 32Bits 32Bits 1bit Zero MSB LSB Zero 1bit Zero MSB LSB Zero QS5100 6-3. Power Consumption Items Standby IDD & Operating Power Down Mode Symbol ICCST/ ICCOP ICCPD 3.0V 45 Max 10 Digital FX LSI Xin = 11.2896 MHz 3.3V 50 Unit mA uA 7. Package Dimension QS5100 Digital FX LSI A. APPENDIX A-1. DFX Module Solution A-1-1. DFX Module Overview DFX-MA4 Digital FX Presets ADJUST Control Level Control DSP arithmetic Ext.DRAM AD Converter DA Converter S/N(A-weight) Dynamic range Frequency passband Sampling Frequency Max.Input voltage Max.Output voltage Input Impedance Analog Input Analog Output Power Supply Power Consumption 1. Delay; Delay Time 2. Chorus: Speed 3. Flange: Speed 4. Reverb; Volume 4 Presets Rotary Linear Volume DFX-MA16 16 Presets Rotary Encoder, Gray Encoder FX Level, Reverb Level 24bit MAX 256KWORD AK4554VT(AK) 90dB 90dB 20Hz ~ 20KHz 32 ~ 48KHz 1 Vrms (Normal 300mVrms) 1 Vrms 12KOhm Mono/Stereo Stereo DC 5V 160mA ( DC IN = 9V,VDD =3.6V Fs = 48Khz ) 1 Vibratone 2 Delay - 150ms 3 Delay - 300ms 4 Delay - 500ms 5 Reverb - Room 6 Reverb - Hall 7 Reverb - Spring 8 Reverb + Delay2 9 Fast Chorus 1 0 1 1 1 2 1 3 1 4 1 5 Deep Chorus Chorus + Delay Chorus + Reverb Flange 1 (Fast) Flange 2 (Slow) Flange + Reverb 1 Flange + Chorus + 6 Delay + Reverb Dimensions 50 x 45mm *A-1 preliminary rev 1.1 - module specs may change without notice! QS5100 Digital FX LSI A-1-2. Pin Descriptions Part_Name/ Pin_No PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 J2 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN1 PIN2 J1 PIN3 PIN4 PIN5 PIN6 PIN1 PIN2 J3 PIN3 PIN4 PIN5 PIN6 PIN NAME VCC + 5V AGND AUX IN1 AUX IN2 AGND AUX OUT1 AUX OUT1 3.6VREF FX MODE FX LEVEL REV LEVEL N.C SCK MISO MOSI NC RESETB GND GPIO5/RXD GPIO6/TXD GPIO7/ADC_IN6 GPIO8/ADC_IN7 GPIO9/ADC_IN8 GND MA4 FUNCTION +5V POWER SUPPLY ANALOG GROUND AUDIO INPUT,SINGLE ENDED MODE AUDIO INPUT,SINGLE ENDED MODE ANALOG GROUND AUDIO OUTPUT,SINGLE ENDED MODE AUDIO OUTPUT,SINGLE ENDED MODE CONTROL PORT REFERENCE VOLTAGE OUT, 3.6V FX MODE CONTROL FX VOLUME REVERB LEVEL MA16 FUNCTION N.C ( Control Port /ADC IN ) SPI BUS MASTER CLOCK INPUT SPI BUS MASTER INPUT SPI BUS MASTER OUTPUT SPI RESET Ground Reserve Control Port/USART INPUT Reserve Control Port/USART OUTPUT Reserve Control Port/ADC IN Reserve Control Port/ADC IN Reserve Control Port/ADC IN Ground *A-1-2 preliminary rev 1.1 - module specs may change without notice! QS5100 Digital FX LSI A-1-3 DFX Module Application Schematic (DFX MA4 Type) *A-1-3 preliminary rev 1.1 - module specs may change without notice! QS5100 Digital FX LSI A-1-4 DFX Module Application Schematic (DFX MA16 Type) *A-1-4 preliminary rev 1.1 - module specs may change without notice! QS5100 A-1-5 MA16 Module Dimension Digital FX LSI A-2. Revision History Date 2005/8/15 2006/3/6 2006/4/13 First edition Rev 1.1: Appendix A-1 Changed 6-3 and Added to A-1-5 MA16 module dimension (Ver 1.2) Description |
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